1. Field of the Invention
The invention relates to an input buffer, and more particularly, to an input buffer with less power consumption.
2. Description of the Related Art
Nowadays, in advanced CMOS (Complementary Metal-Oxide-Semiconductor) processes (such as 28 nm processes), the gate oxide break-down voltage of MOS transistors are lower as compared with previous processes (such as 40 nm processes). The voltage differences between the gate and source/drain of the MOS transistors (Vgs or Vgd) may be required to remain below about 1.8V for devices fabricated by advanced processes. High voltage devices cannot be manufactured by the advanced CMOS processes. For example, 3.3V devices are not manufactured by the 28 nm processes. In addition, lower supply voltages such as 1V may be desirable in advanced ICs (integrated circuits) to save power. However, some peripheral components or other ICs may still operate at high voltages, such as 3.3V or 2.5V. The signals generated the peripheral components or other ICs may have high voltage levels. When the MOS transistors designed to work with lower supply voltages receive these signals, the MOS transistors may not operate appropriately, and they may be damaged by the high voltage levels. Thus, a circuit is provided to serve as an input buffer for converting high voltage levels to lower levels before the signals are received by internal circuits of the ICs. However, previous input buffer circuits may have current paths which induce leakage currents, which increases power consumption and are especially critical in portable devices.